1. Field of the Invention
The present invention relates to the field of integrated circuit packaging. In particular, the present invention relates to ultra thin and leadless surface mount packages.
2. Background Art
Prior art integrated circuits are packaged in plastic packages in which the integrated circuit is fully sealed in the packages. Such fully sealed packages typically have a minimum thickness of 2.0 millimeters. When mounted on a printed circuit board, the top of these packages stands at least 2.0 millimeters high in relation to the surface of the printed circuit board. The height is typically more than 2.0 millimeters since additional space is consumed by pins typically protruding from the bottom of the fully sealed packages. An example of this type of prior art package is a Plastic Pin Grid Array (PPGA). FIG. 1 shows the bottom view of a prior art PGA. As shown in FIG. 1, an array of pins 10 protrude from thee bottom of the package. Pins 10 penetrate holes drilled in a printed circuit board (not shown). Pins 10 are then soldered to conductive patterns laid out on the top and bottom surfaces of the printed circuit board.
Recently, surface mount packages have dispensed with the requirement of pins protruding from the bottom of the package. Instead, surface mount packages use leads that are designed to lie flush with the surface of the printed circuit board. Examples of such surface mount packages are a "Thin Quad Flat Package" (TQFP) and a "Very Thin Small Outline Package" (VTSOP). An example of a typical prior art TQFP is shown in FIG. 2. FIG. 2,shows a side view of a TQFP 12 in which side views of only two leads 14 and 16 are shown for the purpose of illustration. Other leads 18 in the TQFP are identically configured and have the same appearance as the two exemplary leads 14 and 16 when viewed from the side. As shown in FIG. 2, each lead 14 or 16 is shaped so that it inclines toward the surface of the printed circuit board (not shown) and then lies flat on the surface of the printed circuit board.
As shown in FIG. 2, the TQFP typically occupies about 1.2 millimeters of vertical space. This space cannot be reduced to any significant extent since the thickness of the molded body of a TQFP limits the minimization of the vertical space occupied by the TQFP. In other words, the thickness of the molded body 22 of TQFP 12 represents the minimum thickness that can be achieved with the TQFP regardless of how leads 18 are designed.
Other prior art attempts at minimizing the vertical space occupied by an integrated circuit package have also reached their limits. FIGS. 3A through 3D illustrate different prior art integrated circuit packages. FIG. 3A is a Flat Pack (FP) package. As seen in FIG. 3A, leads 26 protrude from the sides of molded body 27 of FP 28. Typically, a rectangular opening is made within a printed circuit board (not shown) and FP 28 is placed inside the opening and is supported by leads 26 which are soldered to the surface of the printed circuit board. Accordingly, the bottom half of body 27 no longer adds to the height of FP package 28. However, one of the drawbacks of FP 28 is that an opening must be made in the printed circuit board. This results in several disadvantages. For example, creating a hole in the printed circuit board causes a reduction in the available area for laying out conductive patterns on the top and bottom surfaces of the printed circuit board. Further, creating a hole in the printed circuit board results in additional cost in designing and manufacturing the printed circuit board. Another drawback in using FP 28 is that the bottom half of molded body 27 extends beyond the bottom surface of the printed circuit board. Accordingly, additional space below the bottom surface of the printed circuit board is required to provide clearance for the bottom half of body 27. Thus, although FP 28 stands lower than other packages having a body of the same thickness, FP 28 extends below the surface of the printed circuit board, therefore requiring a bottom clearance. FIG. 3B illustrates a Ceramic Quad Flat (CQF) 29 which is a variation of FP 28. CQF 29 suffers from the same disadvantages suffered by FP 28.
FIG. 3C illustrates a Leadless Ceramic Chip Carrier (LCCC) 30. LCCC 30 is an example of a fully sealed surface mount package. The entire thickness of molded body 31 of LCCC 30 stands above the printed circuit board. As stated above, this vertical space is typically no less than 1.2 millimeters. FIG. 3D is another example of a surface mount package called a Ceramic Leaded Chip Carrier (CLCC) 32. The leads of CLCC 32 are similar to leads 18 of TQFP 12 shown in FIG. 2. As with TQFP 12 and LCCC 30, molded body 33 of CLCC 32 also stands entirely above the printed circuit board, thus requiring a clearance of at least 2.0 millimeters.
Another recent prior art surface mount package is the OverMolded Pad Array Carrier (OMPAC) 34 shown in FIG. 3E. As shown in FIG. 3E, an array of solder balls 35 is arranged on the bottom surface 36 of OMPAC 34. The array of solder balls interfaces with a printed circuit board. The advantage of OMPAC 34 over "leaded" surface mount packages is that OMPAC 34 eliminates concerns regarding lead coplanarity and skew. However, as with all the prior art surface mount packages discussed above, OMPAC 34 requires at least a 2.0 millimeters of height clearance above the surface of the printed circuit board on which OMPAC 34 is mounted. This is because, like the prior art surface mount packages discussed above, OMPAC 34 is fully molded and the full thickness of the molded body of OMPAC 34 stands above the printed circuit board.
Use of the prior art surface mount packages is generally limited to larger form factor electronic systems, including Personal Computer Memory Card International Association (PCMCIA) Type III (10.5 millimeters) disk drives, modules and cards. However, as portable computing systems are designed around smaller form factor electronic systems, such as those conforming to PCMCIA Type II (having a thickness of 5.0 millimeters) and PCMCIA Type I (having a thickness of 3.3 millimeters) standards, there is a need for integrated circuit packaging technology that is compatible with these smaller form factor electronic systems. Although the prior art has attempted a "Chip On Board" (COB) technology as an option for small form factor packaging, the technology suffers from several disadvantages. First, it is difficult to test the dies or determine the number of good dies mounted on printed circuit boards. Second, the cost of converting manufacturing lines to produce chips on boards is extremely high and has thus prevented chip manufacturers to pursue the COB technology. Thus, there is still need in the art for a single package solution that is less expensive to produce and easier to test (for example, easier to test for Known Good Die, or test at full temperature range, or at full speed) than the COB technology.
Thus, there is need in the art for a surface mount package with a substantially reduced thickness so as to permit integrated circuits to be effectively used in computer card modules and other applications where overall height is very limited. Specifically, there is need in the art to substantially reduce the 2.0 millimeter height of the prior art surface mount packages.